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HCF4515B
OUTPUT "LOW" ON SELECT 4-BIT LATCH/4-TO-16 LINE DECODER
s s s s
s s
QUIESCENT CURRENT SPECIF. UP TO 20V STROBED INPUT LATCH INHIBIT CONTROL INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
SOP
ORDER CODES
PACKAGE SOP TUBE HCF4515BM1 T&R HCF4515M013TR
DESCRIPTION HCF4515B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in SOP package. HCF4515B consists of a 4-bit strobed latch and a 4 to 16 line decoder. The latches hold the last input data presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 1 regardless of the state of the data or strobe inputs. The decode truth table indicates all combinations of data inputs and appropriate selected outputs.
PIN CONNECTION
September 2002
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IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 3, 21, 22 11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14, 13, 16, 15 23 12 24 SYMBOL NAME AND FUNCTION
STROBE Strobe Input DATA 1 to 4 Address Inputs S0 to S15 Multiplexer Outputs (Active HIGH)
INHIBIT VSS VDD
Enable Input Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
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LOGIC DIAGRAM
TRUTH TABLE
INPUTS STROBE INHIBIT L L L L L L L L L L L L L L L L H
X : Don't Care
SELECT OUTPUT S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 ALL OUTPUTS "L"
A L H L H L H L H L H L H L H L H X
B L L H H L L H H L L H H L L H H X
C L L L L H H H H L L L L H H H H X
D L L L L L L L L H H H H H H H H X STROBE = "H" Refer to truth table STROBE = "L" Data at the negative going transition of strobe shall be provided on the each output while strobe is held low.
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Strobe or Data Min. Value (*) Typ. 485 185 135 250 110 85 100 50 40 125 50 35 75 35 20 Max. 970 370 270 500 220 170 200 100 80 ns Unit
tPHL tPLH Propagation Delay Time
tPHL tPLH Propagation Delay Time
Inhibit
ns
tTHL tTLH Transition Time
ns
tW
Strobe Pulse Width
tsetup
Setup Time
250 100 70 150 70 40
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C (1) : If more than one unit is cascaded. tr should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
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WAVEFORM : SETUP TIME and STROBE PULSE WIDTH (f=1MHz; 50% duty cycle)
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SO-24 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 8 (max.) 0.291 0.020 15.60 10.65 0.35 0.23 0.5 45 (typ.) 0.598 0.393 0.050 0.550 0.300 0.050 0.614 0.419 0.1 TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. TYP. MAX. 0.104 0.008 0.096 0.019 0.012 inch
L
a2
e3 D
E
24
13
1
1
2
F
a1
s
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b1
PO13T
b
e
A
C
c1
HCF4515B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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